What percentage imbalance causes a differential type overload to trip?

What percentage imbalance causes a differential type overload to trip?

The LSIS MT Type overloads meet IEC 60947-4-1. Reference to the below excerpt in regards to trip time with phase loss.

8.2.1.5.2 Limits of operation of three-pole thermal overload relays
energized on two poles
With reference to table 4:
The overload relay or starter shall be tested in its enclosure if normally fitted. With the relay
energized on three poles, at A times the current setting, tripping shall not occur in less than
2 h, starting from the cold state, at the value of the ambient air temperature stated in table 4.
(Table 4 `A` multiple of current setting states 2 poles at 1.0 times the current setting, the third pole at 0.9)

Moreover, when the value of the current flowing in two poles (in phase loss sensitive relays,
those carrying the higher current) is increased to B times the current setting, and the third
pole de-energized, tripping shall occur in less than 2 h. (Table 4 `B` multiple of current setting is 2 poles
at 1.15 current setting, third pole at 0.0.)

The values shall apply to all combinations of poles.

In the case of thermal overload relays having an adjustable current setting, the characteristics
shall apply both when the relay is carrying the current associated with the maximum setting
and when the relay is carrying the current associated with the minimum setting.